Interdata Architecture 32-bit System Differences

Historical Overview

16-Bit Prehistory

Interdata started out building 16-bit machines. They all used same basic instruction set but a few instructions weren't implemented in all models.

There were several 16-bit model number series:

The last two, not surprisingly, were contemporaries of the earlier 32-bit systems.

The 16-bit opcode mnemonics appear to anticipate the 32-bit systems. For example, the instruction that loaded a 16-bit register from a 16-bit memory location was LH - Load Halfword. This was not the result of assigning new mnemonics after the introduction of the 32-bit systems. Sales literature for the model 4, the first 16-bit system, uses the halfword mnemonics. A likely explanation is that the opcode mnemonics were chosen to resemble IBM 360 mnemonics for 16-bit operations. Oral tradition claims that the early systems were marketed as less expensive alternatives to IBM 360 mainframes for teaching programming.

It is possible, with considerable care, to create a binary that runs on both 16 and 32-bit Interdata systems. The "common mode" diagnostics are examples.

It is easier, but still requires care, to write assembler source that can be assembled to run on either 16 or 32-bit systems.

The standard OS/32 assembler, CAL/32 (Common Assembly Language/32), will cross assemble for a 16-bit target.

7/32

The 7/32 was the first 32-bit Interdata bit machine. At the time of its introduction there were quite a few 16-bit minicomputers available, and the limits of a 64KB address space were being felt. One approach was to implement a memory paging/mapping system that allowed more memory to be configured on the system than could be addressed at any one time (such as was done with the PDP-11). Interdata chose to go a different route with the 7/32 and built a 32-bit machine. Memory relocation/protection hardware (MAC) was an option.

Legend has it that the 7/32 was a 7/16 HSALU (a 16-bit machine) with different microcode. The 7/32 definitely did have a 16 data bit memory system, requiring double reads or writes to complete 32-bit memory accesses. Early 7/32 systems did have a 16-bit emulation mode, but little or no software made use of it, with the exception of some diagnostics.

The 7/32 used 32KB or 64KB core memory boards.

8/32

The 8/32 was the first completely 32-bit system. It was a higher performance alternative to the 7/32, which was still offered as a lower cost and performance alternative.

It had:

The 8/32 used the same core memory boards as the 7/32. A full megabyte was 16 boards.

3220

The 3220, was the first 3200 system. It effectively obsoleted both the 7/32 and the 8/32. It introduced most of the 3200 series enhancements over the 7/32 and 8/32 but still had MAC memory relocation hardware similar to the older systems.

The 3220 was originally announced as being upgradeable in the future to 4MB. A simple upgrade never appeared. The 4MB upgrade to the 3220 was going to be the 3224 (briefly), then the 3225 (long enough for some manuals to get printed), and finally became the 3230. Owners of early 3220s were offered a discounted upgrade to a 3230 instead.

Kardios, a third party hardware company, did offer a real 4mb 3220 upgrade.

The 3220 introduced:

The 3220 used 256KB MOS memory boards using 4116 DIP memory chips that required a 12-volt supply.

3240

The 3240 joined the 3220 in the product line as a higher performance system.

The 3240 introduced new memory relocation hardware (MAT) that was capable of addressing 16MB of memory. Configuring more than 2MB required a separate memory cabinet, because the 3240 used the same 256KB memory boards as the 3220. Until higher density memory boards became available the typical 3240 had 2MB of memory configured.

Later, a full 16MB could be configured without a memory expansion cabinet using 3250 memory modified to use the 12V memory power available in a 3240.

The 3240 was notable for the high DMA bandwidth possible.

The model numbers 3242 for a 3240 with two-way interleaved memory or 3244 for a four-way interleaved system are encountered. Most people just said 3240.

3230/3210/3212

The 3230 replaced the 3220 in the product line.

The 3230 had a MAT like the 3240. It was different enough to get a whole new model number.

The 3230 originally used 1MB or 2MB MOS memory boards populated with 4164 DIP memory chips that required a 5-Volt supply. Later, 4MB and 8MB memory boards that used 41256 chips became available.

The 3210 was a lower cost version of the 3230.

The 3210:

The 3210A was the OEM version of a 3210. It came without a cabinet for customers who supplied their own enclosure.

The 3212 was the 3210 enhanced by restoring the cache from the 3230.

3250

The 3250 replaced the 3240 in the product line. The 3250 was basically a 3240 modified to use the same higher density memory boards as the 3230. This eliminated the need for a memory expansion cabinet to configure 16MB of memory.

Like with the 3240, the model numbers 3252 and 3254 were used to differentiate systems with different memory interleaving.

The 3250XP was a 3250 shipped with a 3260 backplane.

3200MPS, 3260

The 3200MPS or 3260 was an asymmetrical multi-processor system with a 3250 type processor for a CPU and modified 3230 processors for attached processors (APUs) or I/O processors (IOPs).

The CPU and memory cabinet was much like a standard 3250 CPU and memory cabinet with a different backplane that allowed the connection of APUs and IOPs.

Up to 9 APUs or IOPs could be configured, three to a cabinet, in additional cabinets. The IOPs were 3230 board sets with different cache, different microcode, no memory, and a "RTSM" link back to the CPU. all processors shared the memory in the CPU cabinet.

This was an asymmetrical system, unlike most current multiprocessor systems, which are symmetrical. The OS ran almost entirely on the CPU. APUs ran user code, IOPs ran device drivers. You could hand map programs to processors, or let the OS do it.

Originally, the only attached processor available was the APU. The IOP was introduced later, and later still was an APU/IOP that could be initialized in either role at boot time.

The 3200MPS introduced considerable model number confusion.

3230MPS, 3230XP

An asymmetric multiprocessor system, much like the 3260, but with a 3230 type processor for the CPU.

3205, 3203

The 3205 was added to the product line as a low end, lower cost system. It integrated the CPU, memory, and a SELCH on one board. It came in a desk-high cabinet like a 3210.

The 3205 required a memory expansion board because the memory bus terminator was on the memory expansion board. A 0MB memory expansion board was available to provide termination for systems that had all memory on the CPU board The memory data bus is only 16-bits wide, like the 7/32. Total memory was originally limited to 4MB, but with third party upgrades could reach 16MB.

The 3205 did not have dedicated floating-point hardware, but did have the floating-point instructions microcoded.

The 3203 was a further reduced cost system that eliminated the need (and even the slot) for a memory expansion card by putting the memory bus terminator on the backplane. The 3203 came in a tower case that looked much like an oversized tower PC.

3280

The 3280 was a complete new design that included a number of enhancements:

3280E

The 3280E was the 3280 design reimplemented in high speed ECL logic. ECL logic is known to be both fast and hot. Pictures of the 3280E show a large vent in the front of the cabinet that is not needed by other systems.

Micro3200, Micro3, Micro5

The Micro3200 systems are reimplementations of the 3280 as a single board. This single board could replace a four board 3280 processor board set and was used in new systems.

3200-2000

The 3200-200 is a reimplementation of the 3280 using a Power-PC processor with 3280 emulation firmware. 3200-2000 boards are available to replace the processor board sets in most 3200 systems.

PSW Bits

BIT 7/32 8/32 3220 3230
3210
3212
3240
3250
3260
3205
3203
3280
0 Reserved CSF Reserved
1-7 Reserved
8 Reserved XM - Enable Extended Memory
9 NAT - Reserved
10 Reserved Reserved LVL - Memory Access Level
11 HW Mode
12 Reserved
13 Reserved FLM - floating-point mask
14 Reserved IIP - Interruptible Instruction in Progress
15 Reserved NT - Nontask
16 W - Wait
17 I - I/O Interrupt mask
18 M - Machine Malfunction Interrupt Mask
19 A - Arithmetic Fault FLU - Floating-Point Underflow
20 Reserved I - I/O Interrupt Mask Reserved I - I/O Int. Mask
21 R/P - Relocation/Protection Mask
22 Q - System Queue Service Interrupt
23 P - Protect Mode
24 R - Register Set Selection
25
26
27
28 C - Carry status bit
29 V - Overflow status bit
30 G - Greater than status bit
31 L - Less than status bit
BIT Notes
0 Listed in 50-022 MODEL 3205 SYSTEM INSTRUCTION SET Reference Manual as "Must be zero; IF SET, CATASTROPHIC SYSTEM FAILURE"

"Bit 0 of the PSW is nown as the CSF indicator and must not be set by the user. If the hardware detects a failure previously identified as impossible to recover from reliably, the system will pull a break into the console service routine and set this bit."

9 This bit is only listed in some hardware docs. While the "Cruncher" was in development there was a rumor that it was going to have two instruction sets, a "Cruncher Native Instruction Set" that would be used to run the "Cruncher Native OS", and a 3200 emulation mode for running OS/32. Intriguing.
10-11 Only early 7/32 systems had halfword mode. With this bit set the 7/32 became a 16-bit machine. No known OS that supports this feature.
Bits 10 and 11 together became a memory access level on MAT and VAT machines. This functioned like the "ring level" in some other architectures. Neither OS/32 nor Edition 7 used this feature. Who knows about Xelos? Support for this feature may be required to pass the MAT/CACHE diagnostic.
15 NT - Non-task. This is an attached processor (APU) feature, used by attached processors in multi processor systems.
19 A - Arithmetic Fault/FLU - Floating-Point Underflow. The name changes between 8/32 and 3200, so does the function.

On the 7/32 and 8/32 the A bit controls traps for both integer divide faults and floating-point underflows. Integer divide errors always cause traps on 3200 systems, the FLU bit only controls floating-point underflow traps.

Also, on 7/32 and 8/32 the updated program counter (points to the instruction after the instruction causing the fault) is reported to the trap handler. This makes it impossible to determine the instruction causing the fault in some circumstances. For all 3200 systems the address of the instruction causing the fault is passed to the trap handler.

20 I - I/O Interrupt Mask, OS/32 happily ignores that this bit is reserved in the 7/32 and 3205 documentation. The 3205 documentation allows this bit to be non-zero. It doesn't have any effect unless multiple interrupt levels are being used. Most machines had all devices on level 0 anyway.

Reserved Memory Locations

Address 7/32 8/32 3220 3230
3210
3212
3240
3250
3260
3205
3203
3280
000-01F SP FP Reg. Save Area Reserved, must be zero
020-027 Machine Malfunction Old PSW
028-029 Console
uProgram
Reserved "Used By Console Service Microcode" Reserved
02A-02B Reserved
02C-02F LM Effective Address Word
030-037 Illegal Instruction New PSW
038-03F Machine Malfunction New PSW
040-043 HW Mode Inter. PSWs Reserved Machine Malfunction Status Word
044-047 Machine Malfunction Virtual (program) address
048-04F Arithmetic Fault New PSW
050-07F Bootstrap Loader and device definition table
080-083 System Queue Pointer
084-085 Power Fail PSW Save pointer Power Fail Save Area Pointer
086-087 Power Fail Register save pointer
088-08F System Queue Service Interrupt New PSW
090-097 Relocation/Protection Fault New PSW
098-09B Supervisor Call New PSW Status Word
09C-0BB Supervisor Call New PSW Location Counters
0BC-0C7 Reserved Reserved
0C8-0CF Data Format Fault New PSW
0D0-2CF Interrupt Service Pointer (ISP) Table
2D0-4CF Expanded Interrupt Service (ISP) Table
4D0-8CF Expanded Interrupt Service (ISP) Table
300-33F Reserved for MAC, if ISP ends at 2CF Nothing Special
500-53F Reserved for MAC, if ISP ends at 4CF
900-93F Reserved for MAC, if ISP ends at 8CF

Registers and Memory

Feature 7/32 8/32 3220 3230
3210
3212
3240
3250
3260
3205
3203
3280
Register Sets 2 2 or 8 8
Address Bits 20 24 24 Task
28 VAT
32 VAT off
Max Memory 1MB 16MB 16M task
256M VAT
4GB VAT off
R/P Hardware MAC 2K MAT 4K MAT VAT
Memory Allocation Increment 256 Bytes 2048 Bytes 4096 Bytes
Memory Technology Ferrite Core MOS DIP (4116, 4164, 41256) MOS SIM, SIP

Data Alignment Checking

Address 7/32 8/32 3220 3230
3210
3212
3240
3250
3260
3205
3203
3280
Fullword Memory Read
xxx00 xxx00 xxx00 xxx00
xxx01 TRAP
xxx10 xxx10
xxx11
Fullword Memory Write
xxx00 xxx00 xxx00 xxx00
xxx01 TRAP
xxx10 xxx10 xxx00 or TRAP
xxx11
Halfword Memory Read
xxxx0 xxxx0 xxxx0
xxxx1 TRAP
Halfword Memory Write
xxxx0 xxxx0 xxxx0
xxxx1 TRAP
Bitfield Alignment
TBT HALFWORD? BYTE BYTE? BYTE BYTE?
SBT
RBT
CBT

Instruction Set

Set 7/32 8/32 3220 3230
3210
3212
3240
3250
3260
3205
3203
3280
Logical Operations
BASE Yes
Branching
BASE Yes
Usual Branch No Yes
BSYNC No Yes
Fixed-Point Arithmetic
BASE Yes
Floating-Point Arithmetic
SP FLOAT Option Option Yes
DP FLOAT No or Option Option
3200 FLOAT No
Unnormal FLOAT No
Math Functions No Yes
String Operations (Comercial Instruction Set)
Commercial No Yes
Vector No Yes
High Speed Data Handling
HS DATA No? Option Yes
Input/Output Operations
BASE Yes
BLOCK I/O Yes No
Status Switching and Interrupts
BASE Yes
Priveledged System Functions No Yes
Writable Control Store
Writable Control Store No Option No Yes
Memory Management
LRA Some Yes
Break No Yes
CDS No Yes
SET Notes
Logical Operations
BASE The instructions found on all systems.
  • L - Load
  • LR - Load Register
  • LI - Load Immediate
  • LIS - Load Immediate Short
  • LCS - Load Complement Short
  • LH - Load Halfword
  • LHI - Load Halfword Immediate
  • LA - Load Address
  • LHL - Load Halfword Logical
  • LM - Load Multiple
  • LB - Load Byte
  • LBR - Load Byte Logical
  • EXHR - Exchange Halfword Register
  • EXBR - Exchange Byte Register
  • ST - Store
  • STH - Store Halfword
  • STM - Store Multiple
  • STB - Store Byte
  • STBR - Store Byte Register
  • CL - Compare Logical
  • CLR - Compare Logical Register
  • CLI - Compare Logical Immediate
  • CLH - Compare Logical Halfword
  • CLHI - Compare Logical Halfword Immediate
  • CLB - Compare Logical Byte
  • N - And
  • NR - And Register
  • NI - And Immediate
  • NH - And Halfword
  • NHI - And Halfword Immediate
  • O - Or
  • OR - Or Register
  • OI - Or Immediate
  • X - Exclusive Or
  • XR - Exclusive Or Register
  • XI - Exclusive Or Immediate
  • XH - Exclusive Or Halfword
  • XHI - Exclusive Or Immediate
  • TI - Test Immediate
  • THI - Test Halfword Immediate
  • SLL - Shift Left Logical
  • SRL - Shift Right Logical
  • SLHL - Shift Left Halfword Logical
  • SRHL - Shift Right Halfword Logical
  • RLL - Rotate Left Logical
  • RRL - Rotate Right Logical
  • TS - Test and Set
  • TBT - Test Bit
  • SBT - Set Bit
  • RBT - Reset Bit
  • CBT - Complement Bit
  • CRC12 - Cyclic Redundancy Check 12
  • CRC16 - Cyclic Redundancy Check 16
  • TLATE - Translate
  • ATL - Add to Top of List
  • ABL - Add to Bottom of List
  • RTL - Remove from Top of List
  • RBL - Remove from Bottom of List
BLOCK I/O RB (Read Block) and WB (Write Block). Dropped in the 3200 series. The 3280 uses the opcode for WB for something entirely different (SLOC).
LRA Some early 7/32 systems didn't implement this instruction, later 7/32 and all other systems did. OS/32 has a test for this at system initialization time, and emulates it if missing.
DP FLOAT Documentation for early 7/32 systems lists only single precision floating-point instructions. Documentation for later 7/32 systems lists them as optional.
3200 FLOAT My term. Mainly register-to-register moves not implemented on the 7/32 or 8/32.
  • LPER
  • LGER
  • LGDR
  • LCER
  • LPDR
  • LCDR
  • STDE
  • LEGR
  • LDGR
  • LDER
Unnormal Float The normal floating-point instructions normalize on load. These instructions load floating-point registers without normalizing. Perhaps this is faster? Useful for folks who want to move non-floating-point values through floating-point registers?
  • LUR
  • LWR
  • LU
  • LW
Writable Control Store Some times called "writable control store", sometimes "dynamic control store". On a processor with this feature a portion of the processor microcode memory can be written. This feature adds four instructions:

  • RDCS - Read Dynamic Control Store
  • WDCS - Write Dynamic Control Store
  • BDCS - Branch Dynamic Control Store
  • ECS - Enter Control Store.
Most end users did not write their own microcode. Most commonly the "Fortran Enhancement Package" (FEP) is used. The FEP implemented common floating-point math functions (square root, transcendental functiosn, etc).
Math Functions The 3280 implements many math functions similar to those in the FEP with their own opcodes.
Commercial String, Zoned Decimal, and Packed Decimal instructions. These instructions were not generally used in Concurrent supplied software until support for the MAC machines was dropped. The C compiler and runtime library seems to be an exception.

Many of these instructions were interruptible.

  • MVTU - Move string translated until
  • MOVE - Move string
  • CPAN - Compare Alphanumeric
  • PMV - Pack and move
  • UMV - Unpack and move
  • MOVEP - Move with default pad
  • CPANP - Compare Alphanumeric with default pad
  • PMVA - Pack and move absolute
  • LPB - Load Packed as Binary
  • STBP - Store Binary as Packed
Vector The 3280 and later processors have vector move and initialization instructions, much like the string move instructions, but operating on word instead of byte quantities.
  • MOVS
  • FILSC
  • MOVV
  • FILVG
  • FILVW
Usual branch The 3280 pipeline would continue to fetch instructions following a conditional branch. If the branch was taken a performance penalty would occur because the pipeline contents would need to be discarded and the pipeline refilled. A "usual branch" instruction is identical to a regular branch except that the pipeline is filled from the branch destination and the performance penalty occurs if the branch is not taken.